急求一份VHDL，verilog的英文文献，***带有中文翻译，在线等，谢谢

Standard Verilog-VHDL

Interoperabili ty

Victor Be r man

Cadence Design Systems, Inc.

1.0 Abstract

During the last few years HDLs have become the driver

behind the move to top down design in the electronic

design industry. Two HDLs, VHDL and Verilog HDL have

become the dominant de facto industry standard HDLs.

Since the industry has made a hugh investment in both

HDLs and there is every indication that each will retain

significant market share for the foreseeable future, it is

critical that there exist a standard methodology for

interoperability between the two languages. This paper

describes the relevant issues for interoperability and suggests

solutions where they currently exist. It further summarizes

the work which needs to be done for a complete

solution and the groups who are involved in achieving this

goal. Please note that the emphasis in this paper is on simulation

since the semantics of the two languages are specijied

only for that discipline. ‘While the importance of other

disciplines such as logic synthesis cannot be underestimated

in the top down design process, the lack of standard

language semantics makes general ***ysis problematic.

2.0 lnteroperability Requirements

The problem of interoperability between VHDL and Verilog

HDL is bounded by the usage scenarios which are significant

to designers. The general problem of

unconstrained design development in both languages is

troublesome but fortunately rarely occurs in industry. The

scenarios which we envision as being of most immediate

importance to the designer are:

A Verilog design which must refcrcnces VHDL models

A VHDL design which must refercnce Verilog models

A VHDL design where Verilog netlists are synthesized.

Design groups tend to adopt a singlc language for development

and then define discrete integration checkpoints to

deal with modcls which were extcmally generated. While

this situation m*** change over timc most current needs for

VHDLNerilog interoperability are driven by ASIC library

availability in Verilog and system lcvel component availability

in VHDL. The specification of high level designs

and test benches in VHDL which require ASIC library

components available in Verilog drive the rcquirement for

verification of synthesized Verilog nctlist in a VHDL simulation

environment. Focusing on these scenarios allows

the problem to be bounded in a manageablc w*** and we

divide it into two major segments

Verilog import

VHDLimport

2.1 Verilog import

Two usage scenarios must be supported. In the first one,

the user is incrementally synthesizing Verilog gate-level

netlists from the VHDL model input and desires verification

of the synthesized netlist with the unsynthesized

VHDL; in the second one, the user dcsires to use a Verilog

modcl as an element of a VHDL design.

In the first scenario, a logic synthcsis tool is used to incrementally

synthesize portions of a largc design into Verilog.

0-8 186-5655-7194 $03.00 0 1994 IEEE

2

Progressively larger and larger portions of the design will

be synthesized. The user will wish to verify the accuracy

of the synthesis output through the use of simulation of

regression tests using the VHDL design with Verilog gatelevel

net lists synthesized from progressively more of the

VHDL design. The use of Verilog within this process

should be hidden as much as possible to the user in this

scenario since the user m*** have little or no knowledge of

Verilog. Thus, the VHDL debugger should be able to displ***

and manipulate the synthesized Verilog netlist as if it

were a VHDL netlist.

In the second scenario, a user will wish to utilize an existing

Verilog design as an element in their VHDL design or

test bench. The user in this case will wish to treat the Verilog

model as relatively fixed. The user should not be

required to know how 'Verilog works, but m*** want some

limited visibility into the model to displ*** important

model data that m*** be: known to exist within the model.

2.2 VHDL import

The scenario of primary importance to potential users of

this functionality is the ability to use externally provided

VHDL models as part (of a Verilog model simulation. The

user in this scenario will, in general, not be knowledgeable

of VHDL. It is expected that the VHDL modcls will be

large, fairly high level models of components such as

CPUs and that the purpose of the simulation will be to

assess the behavior of the Verilog models within the context

of a larger system. In this scenario, the VHDL models

will be treated as "library modules" and will change infrequently,

Verilog models will be the elements under development

and will change rather more frequently and

simulations with different stimuli will be common. The

end user will be unconlcemed about VHDL model implementation

particulars, but m*** want visibility to important

VHDL model data such as register values. The user will

want to access any such values in the same manner as

access to other Verilog data is provided.

3.0 Proposed Approach

The general approach laken is to define an interface or

encapsulation l***er between the unlike language models

so that issues such as synchronization, signal resolution,

and timing concepts can be handled systematically. Due to

the differences in the languages, slightly different strategies

are used for the two types of import. They are

described below.

3.1 Verilog import Approach

VHDL models m*** import Verilog models into a VHDL

design through the use of the foreign attribute defined

in the IEE_1076/93Verilog models to bc incorporated into

a VHDL design will have a corresponding entity-architecture

pair declared in VHDL Ports must all be of the Verilog

logic types as declared in the package XL-STD (this

package is a VHDL definition of the Verilog logic types),

or the types declared in the IEEE 1164 package. In the latter

case, conversions between the Verilog type and the

IEEE 1164 type will be performed according to mapping

rules dcfined later. It is assumed that tools which implement

this approach will have this conversion built in for

efficiency. The architecture body must contain an attribute

specification for the foreign attribute. Semantics associated

wilh any other VHDL language constructs within

the entity declaration or architecture body are ignored. The

Verilog module name within the Verilog input file being

imported must be the same as the VHDI, entity name.

An example of a Verilog module and its corresponding

VHDL shell are shown below:

module vxl-cpu (MemData, MemGrant,

IOBusy, MemRw, MemReq, IOReq,

MemAddr, IOAddr, IOOper) )

inout [31:01 MemData;

input MemGrant, IOBusy;

output MemRW, MemReq, IOReq;

output [16:0] MemAddr, IOAddr;

output [l : 03 IOOper;

...

endmodu 1 e

Figure 7 : Example Verilog input file module. v.

3

library IEEE;

use IEEE.std-logic-ll64.all;

entity vxl-cpu is

port( Memdata:

downto 0)

end ;

)

architecture verilog of vxl-cpu is

The shell model contains only port definitions. The

attribute "simulator" defines the name of the VHDL simulator.

The attribute ''model" is used to specify the name of

the VHDL library, entity, and architecture of your VHDL

model.

Ports declared in the root entity must be either scalars or

Port modes are mapped as follows: VHDL ports of mode

in are mapped to Verilog input pons. VHDL ports of mode

inout are mapped to Verilog inout ports. VHDL ports of

modes out or buffer are mapped to Verilog output port?.

Verilog ports are declared in the same order as they appear

in the corresponding VHDL.

VERILOG SHELL

FOR VHDL MODEL

preceded by a T and the Y's surrounding the extended

Figure 2: Example VHDL design file module.vhd identifier are removed.

created for Verilog input file of Figure 7.

VERILOG MODEL

3.2 VHDL import Approach

Since Verilog does not have a pre-defined attribute such as

Foreign the correspondence between Verilog and VHDL

modules is done by convention using an attribute notation

as shown below:

module vhdl-part

(inA, in8 , outA, outB, inout8)

( * integer simulator = "Leapfrog";

integer model=

"mylib.myentity :myarchitecture"; *) ;

input inA;

input [7:01 in8;

output outA, outB;

inout [ 7 : 03 inout8 :

e ndmodule

FIGURE 3. Model Organization for VHDL import

4

4.0 - SIGNAL RESOLUTION

1

X

Z

Since Verilog and VHDL define signals differently, defining

signal resolution is an essential part of the interoperability

definition. Verilog, signals can be defined as either

compdt or non-compact. Compact values contain just

logically values and no saength information (1, 0, X, or

Z). These values are defined as being strong in strength.

Non-compact values contain both a logical value and

strength information (Stl, WeO, Pul, 63X, etc.).

0 0

1 1

X X

Z Z

The interface between Verilog and the VHDL will only be

defined here for two types of VHDL signals. These are the

IEEE std-logic and vlbit signal types.

The IEEE std-logic has 9 states: U, X, 0, 1,Z, W, L, H,

and -. “U’ (un-initialized) is an unknown. “X” (strong

unknown), “0” (strong zero), “1” (strong one), and “ Z

(high-impedance) are similar to Verilog-XL values. The

“W” (weak unknown), “L” (weak zero), and “H” (weak

one) are weak states. The “-” state is also unknown.

The vlbit has just 4 states: X, Z, 0, 1. The explanation for

these values are the m e as for std-logic. The proposed

mapping tx

std-logic

U

X

1

Z w

L

H

vlbit

X

Z

1

een the two systems is shown below:

non-compact compact

StX X s t3: X

s to 0

Stl 1

HiZ Z

WeX X*

Welo O*

We 1 1”

St X

non -compactcompact

s tx: X

HiZ Z

s to 0

Stl 1

* Weak strength is lost in these cases.

5

Mapping the Verilog compact values into VHDL values is

straightforward as show below:

compact I std-logic vlbit

non-compact I vlbit

any 0

any 1

any X

only HiZ

1

X

Z

Mapping the Verilog non-compact values to VHDL

std-logic is more complex. Verilog strengths of Supply,

Strong, and Pull are mapped to strong std-logic values.

Verilog-XL strengths of Large, Weak, Medium, and Small

are mapped to weak std-logic values. The HiZ strength in

Verilog-XL is mapped to a “Z” std-logic value. A sum

mary of this information is shown below:

non -compac t strength

Supply (7)

Strong (6)

Pull (5)

Large (4)

Weak (3)

Medium (2)

Small (1)

HiZZ

std-logic strength

strong

strong

strong

weak

weak

weak

weak

When Verilog values have ambiguous strength, the mapping

is less intuitive. In Verilog-XL, a net m*** have a

value of 630 (logical value of 0 with a strength between

strong and weak). This value could bc mapped as either a

strong 0 or a weak 0. The mapping uses the maximum

strength. In this case the maximum strength is strong, so

therefore the result will be a strong 0 in VHDL

5.0 TIME RESOLUTION

The Verilog timescale is used to determine the

resolution for communication between Verilog-

XL and Leapfrog. VHDL simulation does not

have any notion of “***allest simulation time

unit” other the what is defined in the VHDL

language (femto-seconds).

The two possibilities are that Verilog has a time

resolution ***aller than that used in the VHDL

model or that the VHDL model m*** have its time

resolution ***aller than that used by Verilog. In the

first case, the VHDL simulator does not have any

problems if it receives Verilog interrupts more

than it sees events in a VHDL model.

In the following discussion, “time tick” means the

instant when a time unit ends and another time unit

begins. There is a problem where the VHDL

activity occurs between the Verilog simulation

time ticks. In this case, the events from VHDL will

be recognized by Verilog at the next simulation

time tick.

SIGNAL FROM VHDL

VERILOG TIME

TICKS I I

SIGNAL PASSED TO

There iVsE LoO Ga possibility that VHDL will schedule multiple events in-between two successive time

ticks. In this case, the latest value is passed to Verilog. Each of these can be erroneous.

SIGNAL FROM VHDL

VERILOG TIME

TICKS

SIGNAL PASSED TO

VERILOG

6

If there is a problem with events from VHDL occurring too rapidly for the Verilog model, increasing

the Verilog time resolution is a remedy. This is done by modifying a ’timescale directive in one of the

Verilog models.

The time resolution for the Verilog simulation could be increased by a factor of 10. Doing this with

the previous two examples, would generate the following waveforms:

SIGNAL FROM VHDL

VERILOG-XL TIME

TICKS

SIGNAL PASSED TO

VERILOG-XL

SIGNAL FROM VHDL

SIGNAL PASSEID TO

VERILOG-XL

By increasing the time resolution within Verilog, the signals between the simulators are passed at

more accurate times. There is a trade-off with making this adjustment. The memory usage m*** be

increased and the simulation’s duration m*** increase.

If the Verilog models do not contain any ‘timescale directive, then a def***lt timescale of lSEC/lSEC

is used. Naturally this will c***se incorrect results. Therefore the ‘timescale directive must be used

when importing models into Verilog.

In such cases a resolution warning message is similar to the following should be issued so that the

modeler understands the situation:

Warning! Event(s) happened in a finer resolution.

7

6.0 SYNCHRONIZATION

Since the model for synchronization of time and event processing

in VHDL and Verilog is somewhat different, it is

important for the modeler to understand the strategy proposed.

Signals which pass between Verilog and VHDL are

updated after both simulators have completed all of their

currently active events. In response, the Verilog and

VHDL simulators will process these incoming events. It is

possible for the new events to c***se more boundary signals

to change. once all of the events are processed, the

boundary signal changes are exchanged again. once again

the simulations will be run in response to the signal

changes. This process is repeated until ALL events are

processed for the current time unit.

This synchronization strategy has a side effect on the

$monitor task output. When Verilog completes all of its

active events, it does not know if it will be called back due

to the VHDL simulator passing changes on their port signals.

Therefore, the $monitor statement outputs a line

when Verilog completes all of its activity. However, the

VHDL simulator m*** pass back some more data and this

can c***se some of the monitored signals to change. In

which case, the $monitor statement will produce another

line of data. This can produce results similar to the following:

450 clk= 1 enable=O data=zz

500 ck=l enable=l data=zz

500 clk=l enable=l data=52

At time 500, Verilog-XL evaluated the signal “enable” and

assigned its new value of 1. Verilog complctcd its evaluations

and printed its monitor statement. The signal change

on “enable” was passed to the VHDL model. Thc VHDL

model responded by calculating a new value for the data

bus. The new value was passed back to Vcrilog-XL. Since

Verilog-XL was also monitoring the data bus, it produces a

new output line when it changed.

Another issue conceming synchronimtion deals with

event order dependencies. The events from the VHDL

model will alw***s change after all of the Verilog events

are processed.

my-vhdl vhdll( .... ,data , ...) ;

my-verilog vlogl( .... , clk , ...) ;

alw***s @(posedge clk) out = data;

In the model above, if both “clk” and “data” change during

the same time slice, the old value of “data” will alw***s be

clocked. If the VHDL model was modellcd in Verilog,

then it is possible for the new valuc of “data” to be

clocked.

7.0 Conclusions and Future Work

The ideas presented in this paper givc a starting point for a

standard method of interoperability between VHDL and

Verilog. I would like to stress the importance of gaining

industry support for such a common mcthodology before

thc inevitable market forces lead to disparate proprictary

implementation driven approaches which hamper modcl

intcroperability. A very significant amount of work in this

area has already been done at Cadence to solve the technical

problems involved in modeling and simulation for

mixed language systems including VHDL and Verilog. It

is the intention of Cadence to make as much of this material

public as is needed to solve this important problem for

industry.

Currently, a working group under thc ***spices of the IEEE

DASC has begun to investigate the issues involvcd in

VHDL Verilog interoperability. We plan to work closely

with this group and share our findings with them in the

interest of quickly arriving at a useful standard in this area.

Wc feel that a phased approach to the problem has the best

chance for early success and therefore have suggestcd in

this paper that the problems which are confronting design-

8

ers tod*** be solved first before the more general prob- 8.0 References

lems of multi-language design be tackled.

[l } “IEEE Standard VHDL Language Reference Manual

IEEE Std 1076-1987”, 1988, The Institute of Elechcal and

Electronics Engineers, Inc. New York, NY.

[2) “IEEE Draft Standard VHDL Language Reference Manual

IEEE Std 1076-1992B”,1993, The Institute of Elecwical

and Electronics Engineers. Inc. New York, NY.

We are currently prototyping the ideas discussed in

this paper with Cadence’s VHDL and Verilog simulators

md look forward to reporting on the results of

these efforts in the near Ifuture.

131 “Verilog Hardware Description Language Reference Manual.

Version 2.0”. March 1993, Open Verilog International,

San Jose, CA.

9

虚拟磁盘怎么设置?

电脑上虚拟磁盘怎么开？

虚拟磁盘虚拟磁盘就是在本地电脑里面虚拟出一个远程电脑里面的磁盘。感觉像是在本机上的硬盘一样。其实他没在本机上。

网络虚拟磁盘iSISC加大网吧客户机硬盘容量，高速安全稳定iSCSI Cake主要用于网吧共享硬盘服务。

客户端可以通过局域网连接服务器上的iSCSI Cake服务器，在本地虚拟出一块硬盘，以达到通过网络共享服务器硬盘的效果。网吧业主只需要在服务器上的iSCSI Cake里添加目录和安装游戏软件，客户端的本地虚拟硬盘里就有了相应的游戏软件，不需要到每台机器进行安装。

优点：

1、同时iSCSI Cake提供了写保护，不用担心客户端病毒、用户删除和格式化操作影响。

2、跟其他iSCSI服务器软件相比，iSCSI Cake内存和CPU占用率都非常低，安装简单，操作容易，管理方便，是网吧有盘建虚拟硬盘和无盘工作站的首选软件.

3、支持iSCSI标准协议的网络虚拟硬盘

4、支持写保护（超保护）

5、支持IP绑定和端口绑定

6、支持多网卡、多IP地址

7、支持跨网段

8、内存和CPU资源占用少

服务器配置：

120-200台的配置

主机 CPU 2.8G或3.0G，内存1.5G(推荐2G)

硬盘 系统和工作目录用2个IDE 做0阵列；

3个SATA或4个SATA 做阵列（3个可以用5阵列，4个做0+1阵列）

主板 建议用板载双阵列的技嘉945G PRO或GA-8I955X

网卡 千M（机器超过150台建议双千M网卡分流）

Windows Vista 上内置了iSCSI发起程序。

还有一种虚拟磁盘是由内存中划分出一块区域来当作一个临时的磁盘用，在WinPE这种只读系统中用途很大，也可在正常环境中帮助计算机加速。

当我们在运行一些大型的软件，或者是刚刚退出游戏的时候经常会提示“你的虚拟内存过低”的提示，出现这种情况一般是：一：你的物理内存比较小，运行大的软件比较吃力；二：你运行了许多窗口或者是游戏的时候物理内存分配不过来。当出现这个的时候，我们的系统就会用我们的硬盘空间当成虚拟内存来执行一些操作，那么如何设置我们的虚拟内存呢，在这里我把我个人的经验向大家介绍一下，希望对大家有所帮助，当然这不是真正解决内存问题的办法。

虚拟内存设置的通用原则：虚拟内存最小值是物理内存的1到1.5倍；虚拟内存***值是物理内存的2到2.5倍。

***步：我的电脑右键属性

第二步：属性界面里的“高级”

第三步：高级下面的性能里的设置

第四步：再点一下“高级”

第五步：可以看到最下面虚拟内存，我们点击“更改”按钮”

第六步：这是没有设置虚拟内存的界面

第七步：虚拟内存一般设置C盘之外的硬盘上，选择你剩余空间比较大的硬盘，那么我选择了E盘，再点一下下面的自定义大小

第八步：输入最小值与***值之后点击一下右下角的设置按钮

第九步：会弹出一个重新启动计算机的提示，点确定

第十步：需要我们确认重启电脑，如果还有其它程序在运行可以点“否”。

当我们下次重新启动电脑的时候，我们可以按著以上的操作步骤看到虚拟内存已经设置成功了。

虚拟内存的设置只是针对一些内存比较低的用户，一般物理内存在一G以上的用户就不用设置了。

虚心还教您一种办法，那就是让系统管理虚拟内存的大小

***步：在原有的虚拟内存驱动器上点一下，再点下面的“无分页文件”，再点右侧的“设置”，这样是取消原来的设置。

第二步：选择要设置的“驱......

虚拟磁盘是什么？怎么安装？

1，虚拟硬盘速度快，现在的内存容量一般都在1024MB以上了，而很多朋友用电脑只是进行上网、处理文字、玩游戏等操作，内存并没有得到充分利用。

2，依据内存的访问速度远远高于硬盘这一点，我们就可以在内存中虚拟出一个或者多个磁盘，这样就可以加快顶盘的数据交换速度，提高电脑的运行速度，虚拟硬盘就是用内存中虚拟出一个或者多个磁盘的技术。

3，和虚拟内存一样，内存的速度要比硬盘快得多，利用这一点，在内存中虚拟出一个或多个硬盘就可以加快磁盘的数据交换速度，从而提高的运行速度。

所谓虚拟硬盘是利用软件在内存中虚拟出一个或者多个磁盘的技术。由于内存的速度比硬盘快得多，另外大容量内存的价格又很便宜。内存的速度要比硬盘快得多，就要利用这一点，在内存中虚拟出一个或多个硬盘就可以加快磁盘的数据交换速度，从而提高电脑的运行速度。

安装如下：

1、右击“计算机”选择“管理”选项，弹出“计算机管理窗口”，选择“磁盘管理”， 然后点击“操作”菜单中的“创建VHD选项”。

2、弹出创建和附加虚拟硬盘设置框，选择浏览。

3、从弹出的对话框中选择一个位置，用于保存新建的虚拟磁盘文件。

4、虚拟硬盘大小设置框中输入虚拟磁盘的大小。

5、点击确定，此时会从桌面右下角弹出提示，稍后会提示安装完成。

6、安装完成后，会在磁盘管理界面中出现刚刚新建的磁盘：磁盘1，右键“磁盘1”从弹出的菜单中选择“初始化磁盘”。

7、从弹出的初始化磁盘设置框中设置参数，点击确定。

8、右键磁盘分区，新建简单卷操作。

9、弹出新建简单卷向导。点击下一步。

10、设置磁盘上简单卷的大小。这个大小与开始设置的磁盘文件大小有一定的出入，按提示的设置就可以了。

11、设置卷标，分配一个现在没有用到的磁盘驱动器号。

12、设置格式化该分区。

13、设置完成后系统会对磁盘刚刚的设置进行操作。如格式化完成。

14、查看新建的虚拟磁盘：打开我的电脑，可以从界面上看到，多出了一个新加卷G盘，这就是刚刚添加的虚拟磁盘了，此时便可以打开这个G盘进行读写操作了。

如何给硬盘设置虚拟内存

可以在桌面上用右键单击“我的电脑”图标，点“属性”，在弹出的窗口中点“高级”选项卡，在“性能”区域中点“设置”按钮，点击“高级”选项卡，在“虚拟内存”区域内点“更改”按钮。这时，在窗口中的上半部分是选择虚拟内存要存放的分区，选择后，在下边点“自定义大小”，将“初始大小”和“***值”框中输入要设置的虚拟内存大小（单位为兆字节），然后点“设置”按钮，最后点“确定”按钮关闭窗口就可以了。

推荐将虚拟内存保存的分区设置到非系统分区中，而系统默认的保存分区是系统分区，这时，可以先在上面说的有分区列表的设置窗口中选中C盘，然后点下边的“无分页文件”，点“设置”按钮，在列表中点一下其他的非系统分区，例如D盘，然后点“自定义大小”，设置一下最小和***值后，点“设置”按钮就可以了。***值和最小值推荐设置成一样大小的数字，这样，可以有效减少磁盘碎片的形成而造成的系统性能和运行速度的下降。默认的虚拟内存的大小一般是物理内存的1.5倍，你的是2G内存，默认就是3G大小的虚拟内存可以将初始大小和***值都设置为4096，也就是4G就可以了。

如何设置虚拟硬盘存储？

VMware和Hyper-V都采用了虚拟硬盘方式(VHD-virtual hard disk)，虚拟机的硬盘本质上都是作为一个文件来存放的。如果希望为某台虚拟机提供存储空间，您需要做的仅仅是创建一个VHD文件并把它链接到虚拟机。然而，当真正涉及操作细节时会有大量的问题产生。虽然创建一个VHD文件本身并不是非常的困难，但是有些时候会遇到各种各样的问题。这些文件必须以最适合目标虚拟机的方式来创建。保存VHD文件·通常最经济的选择是直连存储(DAS)，这也是最容易配置的一种方式。DAS最适合于那些仅仅运行了少量虚拟机的主机。这些虚拟机不允许运行那些磁盘访问密集型的应用程序，因为这台服务器上的所有虚拟机都在共享相同的硬盘资源。虽然一般来讲磁盘的存储空间大小不是问题，，而多个虚拟机同时并发的I/O需求则很容易导致性能瓶颈。·网络连接存储(NAS)通常是在网络上保留了一个共享磁盘卷，用于存放虚拟磁盘文件。但是我之前也提到过，最重要的是了解您采用的虚拟化软件自身的限制，例如微软就不支持把Hyper-V的VHD文件保存在NAS系统上。·存储局域网络(SAN)，和NAS一样这是一种基于网络的存储方式，这是两种方式的相似点。它们在架构上***的不同就是SAN是专用于存储系统的网络(它通常也采用了存储系统独有的协议)。在这种方式下，存储子系统的数据流量方式也有别于存储于NAS系统上的文件。采用SAN是最昂贵虚拟存储解决方案，同时也是性能***的方式。物理存储和虚拟存储的区别对于一个新的虚拟化系统管理员而言，掌握物理存储和虚拟存储架构之间的区别往往会遇到一些困难。例如，Hyper-V采用了虚拟的IDE(Integrated Drive Electronics)硬盘控制器模式。虚拟机被要求必须从IDE硬盘上启动，然而这并不意味着Hyper-V虚拟主机上的虚拟机只能选择从本地直连存储系统(DAS)上启动。虚拟机可以选择从一个硬盘驱动器文件启动，而这个文件被映射到一个虚拟的IDE控制器上，从而模拟出虚拟机从IDE硬盘启动的假象。而实际上，该VHD文件本身可以位于本地磁盘(可以是IDE、SATA、eSATA、PATA、SAS或SCSI磁盘)上。同样，把该VHD文件放到SAN系统上也是可以的。***化存储资源池利用率无论您采用了DAS或者是SAN作为虚拟服务器的存储资源池，存储系统的性能都是必须要考虑的问题，因为所有的虚拟机都在争夺硬盘资源。这里有一些方法可以实现对存储资源池的性能优化。对于新用户而言，可以使用RAID0+1存储系统架构。这种架构通过条带化的方式，在提供更佳性能的同时也提供了镜像的容错功能。另外，请确保您的存储阵列采用了10，000rpm的硬盘系统。在SAN当中，如果可能的话尽量为每台虚拟机选择独立的光纤适配器通道。这可以防止光纤通道本身成为连接瓶颈。最后，一些虚拟化平台在创建虚拟硬盘时，可以选择是创建固定大小还是可以动态扩展的磁盘。固定空间的磁盘在创建的时候需要花费更多的时间，但是通常也提供了更好的性能，因为它们采用了物理磁盘上连续的数据块。除去性能降低之外，动态扩展磁盘文件还有一些问题就是可以降低管理员对它的关注，所以可能会发生在扩展后物理卷溢出的情况。当然，所有的这些办法都是在假设物理磁盘资源池里包含了两个或更多虚拟磁盘的前提下。如果可以，请尽量为每个VHD文件创建独立的物理磁盘卷(或LUN)。

如何更改虚拟硬盘设置

Mac虚拟机系统，我们一般采用虚拟硬盘，不同于物理硬盘，虚拟硬盘只是存储在宿主机系统上的一个或多个文件。在Parallels Desktop中，若要对虚拟机硬盘进行更改设置，那么该如何更改虚拟硬盘设置呢？

1.关闭虚拟机。点击菜单栏中Parallels 图标，按选项(Alt)键，按住该键选择“功能”“关闭”；或者如果在屏幕顶部可以看见Parallels Desktop菜单栏，选择“虚拟机”“关闭”。

2.打开“虚拟机”菜单并选定“配置”。

3.在“虚拟机配置”对话窗口，点击“硬件”并在边栏中选择该改“硬盘”。

注意：如果硬盘不存在，可以将其添加到虚拟机配置中。要了解关于如何添加设备的详细信息，请参考如何在虚拟机中添加设备与如何从虚拟机配置中移除添加的设备。

接下来我们就可以对虚拟硬盘进行更改了。

在“源”字段中，指定模拟虚拟机硬盘的虚拟机硬盘文件(.hdd)。可以更改硬盘源：

要使用Boot Camp分区作为虚拟机硬盘，可点击“源”字段并从列表中选定Boot Camp分区名称。

要使用虚拟硬盘文件作为虚拟机硬盘，可点击“源”字段并从列表中选定虚拟硬盘文件，或点击“选择一个镜像文件”并指定进入Mac上所需镜像文件(.hdd) 的路径。

在“位置”栏中，可以指定连接设备的接口类型：

IDE。通过此接口类型，可以连接最多4个虚拟设备（硬盘或 CD/DVD 驱动器）。

SATA。通过此接口类型，可以连接最多6个虚拟设备（硬盘或 CD/DVD 驱动器）。

SCSI。通过此接口类型，可以连接最多15个虚拟设备（硬盘或 CD/DVD 驱动器）。

注意一：Mac OS X 虚拟机操作系统不支持SCSI控制器。在最新的Linux发行版本（例如 RHEL 5.3）中，可能未安装SCSI驱动程序。在此情况下，应在虚拟机的Linux操作系统中安装该驱动程序以使用SCSI控制器。

注意二：无法选择SCSI 7:0位置，因为它被SCSI控制器本身占用。

家用电脑怎么设置虚拟硬盘？

1、使用ramDisk软件就可以设置。

2、虚拟内存盘是通过软件将一部分内存（RAM）模拟为硬盘来使用的一种技术。相对于直接的硬盘文件访问来说，这种技术可以极大的提高在其上进行的文件访问的速度。

3、但是RAM的易失性也意味着当关闭电源后这部分数据将会丢失。但是在一般情况下，传递到RAM盘上的数据都是在硬盘或别处永久贮存的文件的一个拷贝。经由适当的配置，可以实现当系统重启后重新建立虚拟盘。

怎么更改虚拟机虚拟磁盘的类型？

打开虚拟机软件，“编辑虚拟机设置”-点到“硬盘”那一项，然后看右面有个“高级”，这下就看到了吧，或者新建个硬盘重装个系统，，步骤为“编辑虚拟机设置”，下方有个“添加”，然后选择添加“硬盘”，下一步，就有选择IDE，剩下的，你懂的

WIN7怎样在BIOS内设置硬盘虚拟化

虚拟化技术的可以在BIOS中开启，开启方法如下：

1、进入BIOS。开机时按F2或F12或DEL或ESC等键(各电脑有所不同)。

2、进入BIOS后，找到Configuration选项，选择Intel Virtual Technology并回车，将光标移至Enabled，然后再回车，最后按F10保存并退出。

如果找不到Configuration选项，可以试试下面的方法：

(1)某些HP(惠普)电脑进入BIOS后，需要选择SystemConfiguration(系统配置)菜单，然后选择Device Configuration(设备配置)，找到Virtualization Technology，设置为Enabled。

(2)某些联想Thinkpad电脑进入BIOS后，需要选择Security菜单，然后选择Virtualization，设置为Enabled。

(3)某些DELL(戴尔)电脑进入BIOS后，需要选择Processor Settings菜单，然后选择VirtualizationTechnology，设置为Enabled。

如何在虚拟机中添加一个虚拟磁盘？

看下图，打开“虚拟机设置”，点“添加”，按提示选择添加“硬盘”即可。

注：某些旧版本的虚拟机需要先关闭虚拟系统才可以添加新恭件。

电脑的虚拟磁盘不见了，怎么让它显示出来？

虚拟磁盘一般是存放个人文件或者游戏文件的磁盘,是直接与服务器设置相关定,若服务器上的同步软件或者磁盘映射设置出现问题，则可能出现找不到虚拟盘的问题!

因为没有进行初始化的缘故~首先初始化然后划分逻辑盘就可以了。

双人相声剧本（100字内）小学生的

甲: 我们家是吹牛世家!

乙: 我们家还是吹牛专业户呢!

甲: 我们家吹牛不纳税。

乙: 我们家吹牛还不交钱呢!

甲: 不是吹,我一出生就会上厕所。

乙: 爬着去?

甲: 谁刚生下来就会爬呀?

乙: 那怎么去?

甲: 床就当厕所了呗!

乙: 这叫尿床!

甲: 我三个月就会跑。

乙: 那准是个怪胎！

甲: 三个月我妈就上班了,我只好奶奶家/姥姥家两头跑。

乙: 就这么跑呀!

甲: 要说吹牛,我可是没人能比。

乙: 我不信,你敢不敢在这儿比一比?

甲: 在这吹?没问题!

乙: 要说这饭量大,我一顿饭能吃五碗面条！

甲: 我一顿饭能吃八斤水饺！

乙: 哎呀,我发烧了！

甲: 哎呀,我也发烧了！

乙: 晚上睡觉我盖着一床被子,第二天一看,被子烧了个大窟窿！

甲: 晚上睡觉我手里攥着一把玉米,第二天一看,全成爆米花了！

乙: 我比树高！

甲: 我比楼高！

乙: 我头顶天,脚踏地,伸手能抓大飞机！

甲: 我上嘴唇顶着天,下嘴唇顶着地！

乙: 那你的脸呢?

甲: 吹牛的人不要脸了!

乙: 哎!-----

怎么样

植物妈妈还有什么办法送走 自己的孩子最简单的办法

蒲公英妈妈准备了降落伞，把它送给自己的娃娃。只要有风轻轻吹过，孩子们就乘着风纷纷出发。苍耳妈妈有个好办法，她给孩子穿上带刺的铠甲。只要挂住动物的皮毛，孩子们就能去田野、山洼。

豌豆妈妈更有办法，她让豆荚晒在太阳底下，啪的一声，豆荚炸开，孩子们就蹦着跳着离开妈妈；凤仙花妈妈的办法跟豌豆妈妈的办法差不多，凤仙花果实成熟后会炸裂，凤仙花妈妈用这种办法把种子送到四面八方。

扩展资料：

其实在自然界里通过风力来传播种子的植物是非常普遍的。这些植物的种子通常都是非常轻巧的，种子被风吹过的时候质量较轻的一些就能够悬浮在空气中，并顺着风力飘洒到世界各地。

这种通过风力传播种子的植物最出名的就是蒲公英一类的植物，这类植物的果实通常都有伞状的冠毛，其植物的种子也有一些能够适合于借助风力飞翔的特殊构造，当风吹过的时候，种子就会借力飞出果实，然后飘到其他的地方扎根生长。

老舍的真实姓名是什么？代表作是什么？

老舍的真名叫舒庆春。

老舍（1899年~1966年），京派代表，享年66岁，原名舒庆春，字舍予（姓氏要一拆为二），满族，北京人。笔名有“舍予”、“老舍”。1899年2月3日出生在北京西城小羊圈胡同（现名小杨家胡同）,一个满族城市贫民家庭。现代著名作家、杰出的语言大师，被誉为“人民艺术家”。

，字舍予，中国现代小说家、文学家、戏剧家。

老舍的一生勤奋笔耕，创作甚丰。20世纪30年代就成为最有成就的作家之一，著有长篇小说《小坡的生日》、《猫城记》、《离婚》、《牛天赐传》、《骆驼祥子》等，短篇小说集《赶集》等。其《骆驼祥子》问世后蜚声文坛，写了在底层生活者的悲惨生活，标志着老舍现实主义风格的形成，达到了他小说创作的***成就，是我国现代文学史上***秀的长篇小说之一，曾先后被译成十几种外文。20世纪40年代的作品有：长篇小说《火葬》、《四世同堂》等，中篇小说《我这一辈子》，短篇小说集《贫血集》、《月牙集》，以及通俗文艺作品集《三四一》等。中华人民共和国建立后的作品，主要有长篇小说《正红旗下》，长篇报告文学《无名高地有了名》，散文杂文集《福星集》，剧本《龙须沟》、《茶馆》等。老舍以讽刺幽默和诙谐轻松的风格，赢得了人民的喜爱，1951年北京市人民政府授予他“人民艺术家”的光荣称号。

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